In commonly assigned U.S. Pat. No. 4,816,884, issued Mar. 28, 1989, entitled "High Density Vertical Trench Transistor and Capacitor Memory Cell Structure and Fabrication Method Therefor" to Hwang et al., there is described a semiconductor memory cell structure that includes a vertical access transistor formed over a trench storage capacitor. A relatively shallow trench is disposed in an epitaxial layer over a deep trench. A neck structure extends from a top surface of the deep trench to a bottom surface of the shallow trench. Source regions are disposed in the epitaxial layer around the neck structure.
In commonly assigned U.S Pat. No. 4,728,623, issued Mar. 1, 1988, entitled "Fabrication Method for Forming a Self-Aligned Contact Window and Connection in an Epitaxial Layer and Device Structures Employing the Method", to Lu et al., there is described a method of forming a self aligned contact window through an insulator region. The contact window is shown to be useful in a source-to-trench connection that is formed by self-aligned lateral epitaxial growth.
In commonly assigned U.S. Pat. No. 4,507,171, issued Mar. 26, 1985, entitled "Method for Contacting a Narrow Width PN Junction Region", to Bhatia et al. there is described a method for making contact to a narrow pn junction region. A substantially horizontal conductive layer is employed to make contact to a substantially vertical layer so as to have the horizontal conductive layer in electrical contact with a pn junction. The method is said to be useful for fabricating a lateral PNP transistor.
In IBM Technical Disclosure Bulletin Vol. 30, No. 8 January 1988, entitled "Process for Making Contacts or Vias to High Density Fine Lines", Cronin describes a process for making lines of a width below a photolithographic resolution limit and a method for connecting such lines to preexisting contacts or lines.
It is an object of this invention to provide an improved high density dynamic random access memory cell structure.
It is another object of the invention to provide an improved memory cell structure that includes a trench capacitor and an access device formed within a silicon-on-insulator (SOI) region.
It is a further object of the invention to provide an improved DRAM cell that is substantially alignment insensitive, and wherein all images are at groundrule minimums.
A still further object of the invention is to provide a DRAM cell that employs a wordline sidewall contact structure with a buried storage trench capacitor, enabling a memory cell to be constructed within four unit areas.
Another object of the invention is to provide an improved DRAM cell that includes means for providing a substrate contact to a channel region of an SOI device so as to eliminate a floating substrate effect.